`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:02:23 03/25/2009 
// Design Name: 
// Module Name:    opdecoder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module opdecoder(opcode,func,imm,s,cin);

input [5:0] opcode, func;
output imm,cin;

output[3:0] s;



reg imm,cin;

reg [3:0] s;



always @ (opcode or func)

begin
	
imm=0;
	
s=4'b0000;
	
cin=0;

case (opcode)
	
	6'b000000:
		
	begin
		
		case (func)
		    6'b000000:	
						begin
							s=4'b1000;
						end
					6'b001000:	
						begin
							s=4'b1001;
						end
					6'b000011:	
						begin
							s=4'b0010;
							cin=0;
						end
					6'b000010:	
						begin
							s=4'b0011;
							cin=1;
						end
					6'b000001:	
					   begin
							s=4'b0000;
						end
					6'b000111:	
					   begin
							s=4'b0110;
							end
					6'b000100:
					   begin	
							s=4'b0100;
							end
					6'b110110:
						begin
							s=4'b0011;
							cin=1;
						end
					6'b110111:
						begin
							s=4'b0011;
							cin=1;
						end
					6'b101100:
						begin
						   imm=0;
							s=4'b1111;
							
						end
					default	:	
							s=4'b1111;
		endcase
			
	end
		
	6'b000011:
			
	begin
				
		cin=0;
		imm=1;			
		s=4'b0010;
			
	end
		
	6'b000010:
			
	begin
				
		cin=1;
		imm=1;
				
		s=4'b0011;
			
	end
		
	6'b000001:
			
	begin
				
		imm=1;
				
		s=4'b0000;
			
	end
		
	6'b001111:
			
	begin
				
		imm=1;
				
		s=4'b0110;
			
	end
		
	6'b001100:
			
	begin
				
		imm=1;
				
		s=4'b0100;
			
	end

	6'b011110:
	begin
		imm=1;
		s=4'b0010;
	end
	6'b011111:
	begin
		imm=1;
		s=4'b0010;
	end		
	6'b110000:
		begin
			imm=1;
			s=4'bxxxx;
		end
	6'b110001:
		begin
			imm=1;
			s=4'bxxxx;
		end
	default	:	
		s=4'bxxxx;
	
endcase

end



endmodule
